Role

As a Digital Design Engineer, you work with a team working on high-speed connectivity ASIC solutions. You will design, implement, and debug complex digital logic and integrate complex IPs for Credo’s connectivity ASICs. You will work closely with the Software/Firmware, Physical Design, and Applications Engineers to help develop ASICs that meet Credo’s power, performance, and area goals.

Qualifications

• BS/MS in Electrical/Computer Engineering.
• BS degree with 2+ years of relevant experience, or recent graduate with MS degree.
• Knowledge of Verilog/System Verilog, UVM.

Responsibilities

• Microarchitecture and design in Verilog/System Verilog.
• Define and own ASIC design methodologies.
• Integrate complex IPs developed by internal groups as well other vendors.
• Block and Chip level RTL verification and gate-level netlist testing.
• Support other ASIC design activities such as Lint, CDC checks, formal verification, synthesis, and DFT.
• Support back-end engineers with timing-closure and ECOs.
• Chip bring up, validation and debug.
• Support Firmware development and Applications teams.

Skills

• Fluent with Verilog and System Verilog.
• Good oral and written communication skills.
• Knowledge/experience with Python is nice to have.
• Knowledge of ASIC EDA tools such as Synopsys DC, Cadence Incisive (IES), Verdi etc. is nice to have.

Experience

This position is open to recent graduates as well as experienced Digital Design Engineers.

For experienced engineers:

• Experience with RTL design and verification using Verilog/System Verilog is a must.

Experience with at least 3 of the following:

• Experience with Verification using System Verilog (UVM).
• Experience with chip validation and bring up.
• Experience with STA and timing closure.
• Experience/Understanding of Ethernet protocols.

Pay Range: $140,000 - $160,000