Used in Distributed, Disaggregated Chassis (DDC) applications, HiWire CLOS AECs are designed to replace chassis backplanes with front panel interconnect. The LP CLOS AEC 800 is the industry’s first 800G Active Electrical Cable.
The use of AECs enables traditionally homogeneous hardware racks and coupled operating systems to be decoupled, enabling architects to mix-and-match configurations for optimal cost, power, and performance requirements.
The CLOS AECs are offered with 56G/lane and 112G/lane link speeds. The small diameter and light weight of the cables enables them to have a tight bend radius making rack installation and maintenance easy. Designers looking to redirect power to processing and storage can reduce data transport power by replacing AOCs, which average 50% more power than CLOS AECs. At 112G/lane, designers can also reduce DAC port power by 20% by switching to AECs.
The PAM4 LP CLOS AECs are available with QSFP-DD and OSFP connectors, inside which are Credo low power, high performance retimers.
Line : Host | 1:1 Direct | |
Connectors | QSFP-DD : QSFP-DD / OSFP : OSFP | |
Lengths | 0.5m – 2.5m (1x6.8mm) | |
CU Gauge | 32AWG | |
Modulation | PAM4 to PAM4 (Retimer) | |
Link Speeds | 56G, 112G | |
Cable Throughput | 400G, 800G | |
Max Latency | 40ns | |
Integrations | Retimer | |
Power Supply | 3.3V +/- 5% | |
Power Consumption | 400G | 4.5W / end |
800G | 10W / end | |
Operating Temperature | 0°C - 70°C | |
BER | <10-8 (pre-FEC) <10-15 (post-FEC) | |
I2C Management | CMIS v3.0 and v4.0 |
LP CLOS 800 (QSFP-DD)
CAC4XX321D1D-C0-HW
CAC4xx321D1D-D0-HW
CAC4xx321D1D-A0-HW
CAC4xx321D1D-D0-HW
CAC4xx321D1D-A0-HW
LP CLOS 800 (QSFP)
CAC805321A1A-A0-HW
CAC81X321A1A-A0-HW
CAC815321A1A-A0-HW
CAC82X321A1A-A0-HW
CAC825321A1A-A0-HW
LP CLOS 400 (QSFP-DD)
CAC4XX321D1D-C0-HW
CAC4xx321D1D-D0-HW
CAC4xx321D1D-A0-HW
Credo, with partners UfiSpace and Drivenets, presented the World’s largest router, a 350Tb DDC implementation with CLOS AECs for front panel interconnect, at the Open Compute Global Summit.