IP3
Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal and DSP architectures are the foundation for our high performance and low power SerDes technology.
The architectural approach taken by Credo has enabled us to design in
mature fabrication processes yet deliver leading-edge performance and power. Credo was the first to deliver 56G NRZ in 40nm, 56G PAM4 in 28nm and 112G PAM4 in 28nm.
120G Specifications
Applications
Switch Fabric ASIC
Geometry
3nm
Signaling
112G
Reach
LR, MR, VSR, XSR
56G Specifications
Applications
HPC ASIC
Geometry
3nm
Signaling
56G
Reach
LR, MR, VSR, XSR
28G Specifications
Applications
AI ASIC
Geometry
3nm
Signaling
56G
Reach
LR, MR, VSR, XSR