OmniConnect
Credo OmniConnect is a next-generation interconnect architecture designed to break through the memory bottlenecks that limit AI inference scalability. It combines ultra-efficient 112G VSR SerDes with a lightweight AXI framer to deliver high-bandwidth, low-latency, and power-optimized connectivity between compute engines and memory—whether on-die, off-substrate, or across chiplets.
OmniConnect Weaver
Credo’s Weaver is a memory fanout gearbox that overcomes the memory bottlenecks in AI inference workloads as scalability, bandwidth and efficiency demands in data centers continue to rise.
Credo OmniConnect Products
Credo OmniConnect is a versatile AXI-over-VSR SerDes bus that enables both die-to-die interconnect and scale-up networking by connecting multiple compute engines via external chiplets. It incorporates robust telemetry features for reliability and uptime.
Weaver
Rate
112G
Number of Lanes
12
Memory Interface
LPDDR5X
Form Factor
Chiplet
Reach
250mm
Credo OmniConnect Features
As AI inference workloads grow more complex and memory-intensive, memory density and bandwidth have proven to be limiting factors in achieving maximum compute performance. Additionally, inference models and context windows are scaling much more rapidly than memory interfaces. Credo’s OmniConnect solves these challenges through a rich feature set.
Low-cost, low-power memory fanout
Enables cheaper LPDDR memory to achieve high bandwidth and high density for evolving AI inference workloads.
10x boost in beachfront I/O density
Weaver provides 2Tb/s/mm beachfront density compared to 0.18Tb/s/mm for conventional LPDDR5X.
20x increase in memory density
Up to 6.4TB of memory density with Weaver compared to max 256GB using LPDDR5X.
Future-proof compute for memory transition
Allows simple transition from LPDDR5X to LPDDR6 without any change to XPU.
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