Credo IP3

SerDes IP

IP5

Credo designs SerDes IP that optimally balances performance, power and manufacturing process costs and risks. Our unique, patented mixed signal and DSP architectures are the foundation for our high performance and low power SerDes technology.

The architectural approach taken by Credo has enabled us to design in mature fabrication processes yet deliver leading-edge performance and power. Credo was the first to deliver 56G NRZ in 40nm, 56G PAM4 in 28nm and 112G PAM4 in 28nm.

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112G PAM4 Specifications

Applications

Switch Fabric ASIC

Geometry

5/4nm

Signaling

112G PAM4

Reach

LR, MR, VSR, XSR

56G PAM4 Specifications

Applications

HPC ASIC

Geometry

5/4nm

Signaling

56G PAM4

Reach

LR, MR, VSR, XSR

28G PAM4 Specifications

Applications

AI ASIC

Geometry

5/4nm

Signaling

28G NRZ

Reach

LR, MR, VSR, XSR