Will Enable Second Generation 400 Gbps Capable of Longer Distances
In late 2018, Barefoot networks publicly announced the first ever 7nm plus chiplet switch ASIC product – the Tofino 2 chip. This is the start of a market transformation as Ethernet Switch design will begin to embrace disaggregation (such as the chiplet type design) much like the rest of data center market. We will see strong product demonstrations at OFC, OCP, and numerous other shows throughout 2019 as the ecosystem gears up for this important architecture shift. With 7nm available from major foundries, the market will begin to move in this heterogenous direction as a way to higher capacity switch silicon. Not only will this pave the way for 25.6 Tbps and 51.2 Tbps fabrics, we will see increased product agility, lower cost, better power, and more products offerings from chiplet design.
It is important to note that switch ASICs have had both the analog and logic designs put on the same semiconductor chip for over a decade, which forced designers to shrink the analog portion of the design to the same semiconductor process geometry as the logic design. However, since the analog part of chip design is fundamentally different from the logic design, it moves to a different design time-table than the logic design. Chiplets have a huge advantage as the analog part of the design does not have to shrink at the same pace as the logic component. This disaggregation of technology allows for older and proven analog chip components to be packaged along with cutting edge process geometry-based logic chips. As we saw in Tofino 2 chip, the analog component is provided by a different vendor and is on a 28nm or 16nm process geometry, while the Barefoot logic is in 7nm.
Second generation 12.8 Tbps fabrics (defined as 7nm and chiplet architectures vs. 16nm single chip solutions) will also enable Ethernet Switches to take on metro deployments that today are primarily served by stand-alone optical transport gear. This will significantly increase the addressable market for Ethernet Switch products and vendors, something that is generally a good thing for the Ethernet ecosystem, customers, and industry.
The speed of product innovation in 2019 will be fast-paced. With 56 Gbps SERDES chips just now starting to ship, we will see many next generation 112 Gbps SERDES announcements in 2019. This, in turn, will help set up 2020 to be a transition year to the shipment of higher speeds, just in time to meet the demand of new high-bandwidth workloads such as Artificial Intelligence (AI) and video game streaming. AI will continue to see massive investment dollars in 2019 and beyond, increasing demands on the network, while game streaming will come to life as Microsoft and Sony deliver Their next consoles. These new workloads will significantly impact the network and will cause a change in network evolution, data center speeds and network programmability.
One of the first use cases for 400 Gbps will be in the aggregation/core part of the network. Cloud providers will look at 400 Gbps and above for connecting their data center properties together. This will cause Data Center Interconnect (DCI) to become a larger part of Cloud CAPEX in 2019 and 2020.
