SerDes IP and Chiplets

Credo’s core SerDes and purpose-built mixed signal DSP technology is offered as licensed IP for customer-specific ASIC designs and as chiplets for integration into Multichip Module System on Chip (MCM SoC) and 2.5D Silicon Interposer designs. Our technology is designed for easy integration, whether of tens or hundreds of SerDes lanes.

SerDes IP

Credo designs SerDes IP that optimally balances performance, power and the costs and risks of the manufacturing process. Our unique, patented mixed signal architecture has enabled us to design in mature fabrication processes yet deliver leading-edge performance and power.

SerDes "Chiplets"

Core and analog logic may not always deploy at the same time, in the same process. Credo’s unique SerDes architecture makes it possible to deliver cost and power-effective solutions in mature process nodes, making the functionality available in chip form for integration with SoCs to overcome the need for matching core logic and SerDes funtionality in the same process node.

Solutions

SerDes IP
Product	Application	Function	Geometry	Signaling	Reach
IP5	Switch Fabric ASIC HPC ASIC AI ASIC	SerDes	5/4nm	112G PAM4 56G PAM4 28G NRZ	LR, MR, VSR, XSR LR, MR, VSR, XSR LR, MR, VSR, XSR
IP7	Switch Fabric ASIC HPC ASIC AI ASIC	SerDes	7/6nm	112G PAM4 56G PAM4 28G NRZ	XSR LR, MR, VSR, XSR LR, MR, VSR, XSR
IP12	Switch Fabric ASIC HPC ASIC AI ASIC	SerDes	16/12nm	112G PAM4 56G PAM4 40G PAM3 28G NRZ	LR, MR, VSR, XSR LR, MR, VSR, XSR LR, MR, VSR LR, MR, VSR, XSR
IP28	Switch Fabric ASIC	SerDes	28nm	28G NRZ	LR, MR

SerDes "Chiplets"
Product	Application	Function	Host Side / Reach	Line Side / Reach
Nutcracker	Switch Fabric ASIC AI ASIC Machine Learning 2.5D Silicon Interposer	DSP Retimer	32 x 112G PAM4 / XSR	32 x 112G PAM4 / MR+
BlueJay	Switch Fabric ASIC AI ASIC Machine Learning 2.5D Silicon Interposer	DSP Retimer	Low Power BoW / XSR	64 x 56G PAM4 / LR