SerDes IP and Chiplets

Credo’s core SerDes and purpose-built mixed signal DSP technology is offered as licensed IP for customer-specific ASIC designs and as chiplets for integration into Multichip Module System on Chip (MCM SoC) and 2.5D Silicon Interposer designs. Our technology is designed for easy integration, whether of tens or hundreds of SerDes lanes.

SerDes IP

Credo designs SerDes IP that optimally balances performance, power and the costs and risks of the manufacturing process. Our unique, patented mixed signal architecture has enabled us to design in mature fabrication processes yet deliver leading-edge performance and power.

SerDes "Chiplets"

Core and analog logic may not always deploy at the same time, in the same process. Credo’s unique SerDes architecture makes it possible to deliver cost and power-effective solutions in mature process nodes, making the functionality available in chip form for integration with SoCs to overcome the need for matching core logic and SerDes funtionality in the same process node.

Solutions

SerDes IP
ProductApplicationFunctionGeometry
Signaling
Reach

  • Switch Fabric ASIC
  • HPC ASIC
  • AI ASIC
  • SerDes
  • 7nm
  • 112G PAM4
  • 56G PAM4
  • 28G NRZ
  • LR, MR, VSR, XSR
  • LR, MR, VSR, XSR
  • LR, MR

  • Switch Fabric ASIC
  • HPC ASIC
  • AI ASIC
  • SerDes
  • 16/12nm
  • 112G PAM4
  • 56G PAM4
  • 28G NRZ
  • LR, MR, VSR, XSR
  • LR, MR, VSR, XSR
  • LR, MR

  • Switch Fabric ASIC
  • SerDes
  • 28nm
  • 28G NRZ
  • LR, MR

SerDes "Chiplets"
ProductApplicationFunctionGeometry
Host Side / Reach
Line Side / Reach

  • Switch Fabric ASIC
  • AI ASIC
  • Machine Learning
  • 2.5D Silicon Interposer
  • DSP Retimer
  • 12nm
  • 32 x 112G PAM4 / XSR
  • 32 x 112G PAM4 / MR+

  • Switch Fabric ASIC
  • AI ASIC
  • Machine Learning
  • 2.5D Silicon Interposer
  • DSP Retimer
  • 28nm
  • Low Power BoW / XSR
  • 64 x 56G PAM4 / LR

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