Role

In this role as the Mixed Signals ATE Test Engineer, you’ll help design and manufacture our next-generation, high-performance, power-efficient DSP based analog devices bringing them from design to mass production. You will be working with design, application engineer, DFT, product engineers, quality engineers, and offshore teams to plan and execute the product rollout operation. We are seeking a dynamic engineer to design and debug ATE programs and hardware for debug, characterization, qualification, and production of our next generation of devices!

Qualifications

• In depth knowledge of Semiconductor Manufacturing Process
• Have proven experience in developments for Automatic Test Equipment (ATE)
• Deep understanding of RF and Analog Fundamental, Design for Test and Manufacturing Concepts
• Expertise in Semiconductor Test Methodology
• Experience working on Digital, Mixed Signal, RF/SOC, & PMIC Devices with hands on VLSI ATE experience. System level experience is a plus
• Strong programming skills for writing and debugging test programs and HW related issues. Proficiency in programming with Scripting languages (ie., Perl/Python) and high level languages (ie., C/C++ or Visual Basic.)
• Validated experience with test equipment (ie., oscilloscope, logic analyzer, BERT, etc)
• Excellent interpersonal skills to work with internal team members and external suppliers to drive project execution
• 5+ years meaningful experience
• You should be a standout colleague, work well independently as well as collaboratively in a team setting
• Bachelor’s Degree in Electrical Engineering or Computer Science/Software Engineering or equivalent is required. Master’s Degree preferred.

Responsibilities

• Develop and document test plan for new devices.
• Design and debug test SW & HW for Production, Characterization & Reliability.
• Debug new silicon.
• Bring quality and efficient test solution for mass production.
• Coordinate test related activities with both internal and external group.
• Evaluate new product’s testability and operability.
• Implement test programs and release into offsite production.

Pay Range: $90,000 - $120,000

Purpose

The purpose of this position is to work on PCB layout for all the projects in US office

Responsibilities

In this role you will design, floorplan, and complete PCB designs. This includes early assessment of effort, initial placements, routing, and final rule verification. Designs are released for manufacturing and require support of DFM and component inquiries. You will have a close working relationship with people from outstanding background and skillsets. An emphasis is on designing power delivery around power converters in addition to high speed signaling.

Qualifications

• 7+ years relevant industry experience of PCB layout design
• Expertise using Cadence Allegro for multi-layout board layout
• Detailed knowledge of PCB manufacturing processes and design rules
• Symbol and footprint generation based on datasheet
• Familiar using OrCAD Component Information Portal (CIP)
• Responsible for the design releases required generation of artwork files

Pay Range: $150,000 - $160,000

Job Description

• Lead verification efforts on PCIe IPs and SoC products
• Architect and build system and unit-level UVM verification environment
• Work with architects to define verification strategy and execution plans
• Review metrics and deliver task with high quality
• Analyze Functional, Code, and Test Plan Coverage
• Drive and participating in Code Reviews
• Identify, drive, and develop efficiency and IP quality improvement initiatives
• Drive root cause analysis and corrective actions for Functional bugs found in Silicon
• Drive projects from start to the finish and conduct Design verification sign-off

Minimal Qualifications

• Master’s degree in Electrical Engineering or related field
• 5 years of industrial experience in Design Verification
• Proficiency in SystemVerilog and Object-Oriented Programming
• Experience in UVM, SVA, VIP, DPI
• Understand verification best practices
• Experience in PCIe protocol stack
• Proficient scripting language in one of: Python, TCL, Shell, Perl
• Self-motivated team worker

Preferred Qualifications

• Experience of overall design verification experience in the ASIC industry
• Experience in a design verification lead or management role
• Strong background in the development of verification environments in System Verilog
• Expertise in constrained random verification methodologies.
• Formal verification experience a plus
• Extensive experience verifying complex designs using UVM
• Experience in CXL, AXI, AHB, USB, I2C, Ethernet
• Experience with verification of Hardware-Firmware interaction is highly desirable
• Experience in digital signal processing

Pay Range: $200,000 - $250,000

Role

Upon joining our team as a Hardware Engineer, you will be directly applying your engineering expertise and working with many cross-functional teams to create next generation interconnect solutions with single-lane rate of 25G, 50G, and 100G connectivity products!

Qualifications

• 5+ years relevant industry experience designing high speed SerDes and FPGA systems
• Master Degree in Electrical Engineering or equivalent
• Strong Electrical Engineering fundamentals (analog/digital design, signal/power integrity, etc.)
• Comfortable in a lab environment using oscilloscopes, spectrum analyzers, network logic analyzer, etc.
• Familiar with PCB design and common electrical interfaces: High speed SerDes, I2C/MDIO buses
• Knowledge in one or more of the following areas: DSP, MCU, FPGA, power (DC-DC converters, power management, low power design)

Responsibilities

• This is a design engineering position that entails working with cross- functional groups to continually open up the boundaries of technology implemented in Credo’s products
• Our goal is to help define exciting product features that help to create better products
• You’ll have the ability to solve challenging engineering problems by selecting components, designing schematics, directing layout and bringing up/ debugging circuits in the lab
• You will have access to state of the art test equipment in labs to perform characterization of your circuits

Skills

• Strong hardware design and project management skills
• Ability to work with cross-functional teams to establish the deliverables on time

Experience

• Must have hands-on experience in prototyping, bring-up, debug and validation
• Experience working with mechanical design and software development teams
• Experience with Cadence Or CAD and Allegro is a plus

Pay Range: $100,000 - $125,000

Role

As a Digital Design Engineer, you work with a team working on high-speed connectivity ASIC solutions. You will design, implement, and debug complex digital logic and integrate complex IPs for Credo’s connectivity ASICs. You will work closely with the Software/Firmware, Physical Design, and Applications Engineers to help develop ASICs that meet Credo’s power, performance, and area goals.

Qualifications

• BS/MS in Electrical/Computer Engineering.
• BS degree with 2+ years of relevant experience, or recent graduate with MS degree.
• Knowledge of Verilog/System Verilog, UVM.

Responsibilities

• Microarchitecture and design in Verilog/System Verilog.
• Define and own ASIC design methodologies.
• Integrate complex IPs developed by internal groups as well other vendors.
• Block and Chip level RTL verification and gate-level netlist testing.
• Support other ASIC design activities such as Lint, CDC checks, formal verification, synthesis, and DFT.
• Support back-end engineers with timing-closure and ECOs.
• Chip bring up, validation and debug.
• Support Firmware development and Applications teams.

Skills

• Fluent with Verilog and System Verilog.
• Good oral and written communication skills.
• Knowledge/experience with Python is nice to have.
• Knowledge of ASIC EDA tools such as Synopsys DC, Cadence Incisive (IES), Verdi etc. is nice to have.

Experience

This position is open to recent graduates as well as experienced Digital Design Engineers.

For experienced engineers:

• Experience with RTL design and verification using Verilog/System Verilog is a must.

Experience with at least 3 of the following:

• Experience with Verification using System Verilog (UVM).
• Experience with chip validation and bring up.
• Experience with STA and timing closure.
• Experience/Understanding of Ethernet protocols.

Pay Range: $140,000 - $160,000

Role

Credo is looking for an Application/System validation Engineer to join our Application Engineering team! This is a fantastic opportunity for you to join our talented team.

Qualifications

• MSEE degree

Responsibilities

• Perform characterization of Credo cutting edge high-speed SERDES for Ethernet and Optical markets
• Perform system level validation for different applications and environment conditions
• Help the Firmware Team to improve the SERDES adaptation algorithm with lab test results
• Manage and resolve customer real application issue
• Provide/Generate application notes for Credo SERDES

Skills

• Knowledge of python scripting and equipment automation control
• Knowledge of data communication and USB and DP protocol (USB3.2/USB4/DP2.0) is a plus
• Knowledge of data communication and networking protocols (IEEE 802.3) is a plus
• Knowledge of DSP concepts and implementation skills is a plus
• Working knowledge of lab equipment like VNA, Oscilloscope, traffic generators etc

Experience

• Experience in high speed interfaces like 10G/40G/100G for Ethernet and Optical market

Pay Range: $100,000 - $140,000