Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology

Credo expands its unique programmable power versus channel reach performance SerDes technology to TSMC N3 and N7/N6 processes

SAN JOSE, Calif.—Feb 01, 2024—Credo Technology Group Holding Ltd (NASDAQ: CRDO) today introduced its newest 112G PAM4 SerDes Intellectual Property (IP) family on TSMC’s industry leading N3 and N7/N6 process technologies.   These two new SerDes IPs complement Credo’s available IP in TSMC’s N5 process technology, which also includes the enhanced N4 version of the 5nm node. This comprehensive SerDes IP family supports a wide range of demands including long reach plus (LR+), long reach (LR), medium reach (MR) and very short reach plus (VSR), for applications including AI, machine learning, high performance compute, switching, security, and optical deployments.

Jeff Twombly, Vice President of Business Development commented, “Credo is committed to delivering industry leading performance combined with outstanding energy efficiency across the newest optimal process technologies and for a wide variety of reaches. By selecting from our broad portfolio of 112G PAM4 IP, our customers can design complex, monolithic chips rapidly and cost effectively for demanding applications.”

“We believe 112G SerDes is the critical technology to enable AI/ML at scale and will be the main driver for Ethernet Switch revenue and port growth over the next three years,” said Alan Weckel, Founder and Technology Analyst at 650 Group. “We anticipate that Credo’s purpose built, energy efficient, optimized low power programmable per reach 112G SerDes architecture will be a key building block for semiconductor companies as they migrate their designs to 800G and 1.6T.”

Credo’s advanced DSP based 112G PAM4 SerDes architectures were developed and proven on TSMC’s 12nm process technology. The 12nm technology was then integrated into Credo’s complete family of 112G per lane connectivity products for both copper and optical applications at 800G and 1.6T port rates. Credo then ported the 12nm, 112G SerDes to more advanced process technology nodes (N7/N6, N5/N4, and N3) – allowing customers to integrate the silicon proven technology into monolithic ASICs and chiplets.

Software programmable innovations allows customers to optimize power and performance on a lane-by-lane basis, unleashing new levels of system level performance. These new 112G PAM4 SerDes IP were designed to meet the growing data needs of high-speed, data-intensive applications. Credo's SerDes technology enables silicon solution providers and OEMs to manufacture custom chip solutions which address new market opportunities, while delivering on critical performance and low-power system level requirements. All Credo IP solutions are supported with evaluation boards, simulation models, characterization reports, reliability reports, design libraries and a complete set of supporting documentation. Customers interested in this new IP should contact

About Credo 

Our mission is to deliver high-speed solutions to break bandwidth barriers on every wired connection in the data infrastructure market. Credo is an innovator in providing secure, high-speed connectivity solutions that deliver improved power efficiency as data rates and corresponding bandwidth requirements increase exponentially throughout the data infrastructure market. Our innovations ease system bandwidth bottlenecks while simultaneously improving on power, security, and reliability. Our connectivity solutions are optimized for optical and electrical Ethernet applications, including the emerging 100G (or Gigabits per second), 200G, 400G,800G and the emerging 1.6T (or Terabits per second) port markets. Credo products are based on our proprietary Serializer/Deserializer (SerDes) and Digital Signal Processor (DSP) technologies. Our product families include Integrated Circuits (ICs) for the optical and line card markets, Active Electrical Cables (AECs) and SerDes Chiplets. Our intellectual property (IP) solutions consist primarily of SerDes IP licensing.

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