At Credo, we recognize that Generative AI and the disaggregation of traditional servers with technologies such as CXL are having a massive impact on hyperscale data centers (HSDCs).
Throughout the show, the OCP Experience Center, was an extremely popular attraction showcasing how HSDCs will be built in 2024, and provided a glimpse into how they may change in 2027 and beyond. With our “Rack and Power” focused partners, we showcased a row of compute servers with new automation technology, a leaf connectivity rack, a row of AI servers, and a spine/routing layer with full interconnect.
Attendees were able to see first-hand how connectivity can evolve to support the needs of generative AI and general compute over the next four years, including using CXL based scale-out backend networks and memory sharing via rack-scale CXL.
During the show, Credo introduced the HiWire Pluggable Patch Panel (P3), providing service providers and hyperscalers the freedom to decouple pluggable optics from core switching and routing hardware using Credo’s HiWire Active Electrical Cables (AECs).
Don Barnetson, VP Product, HiWire AECs, Credo announced that “the Credo HiWire P3 box allows you to decouple the optics that you are using from the switching and routers to support optics that don’t have software compatibility and routers that don’t have the power and cooling to support. You now have the choice of whichever coherent optics you want to use in your system, including up to 800G optics.”
During OCP Credo also showcased a live 1.6T OSFP-XD AEC demo that showed BER rate and a partner demo that utilized AOI modules and an EXFO tester in an 800G-SR8 OSFP demo.
Many of the hot topics during the Summits dialogues, workshops, and sessions involved AI, including VP of Product, Don Barnetson’s presentation on Generative AI and the Outsized Role of SerDes. The presentation emphasized the transformative nature of AI/ML technology and its ability to achieve up to 20 times the density of traditional front-end Ethernet solutions. SerDes technology, which constitutes around 25% of AI power consumption, was highlighted as a critical focus area for sustainability efforts, while SerDes power modes that have the potential to yield up to an additional 50% power savings, resulting in a combined opportunity to reduce SerDes power consumption by up to 75%.
Continuing the AI discussion, Credo’s session by VP of Business Development, Jeff Twombly, The Rise of Chiplets in Advanced AI/ML/HPC SoC’s, covered critical SerDes IP developments, chiplet productization, and testing considerations to enable volume at scale. The discussion included how Credo’s expertise and infrastructure is equipped to enable more chiplet variants required for emerging I/O standards, such as for UCIe. In addition to technical aspects, the presentation emphasized the importance of collaboration, and highlighted the pivotal role chiplets play in shaping the future of AI/ML/HPC innovation.