SerDes "Chiplets"

Core and analog logic may not always deploy at the same time in the same process, which may slow the pace
of your next generation solutions.

Credo’s unique SerDes architecture makes it possible to deliver cost and power-effective SerDes solutions manufactured in mature process nodes, and have them available in chip form for integration with SoCs, Chiplets overcome the need for matching core logic and SerDes IP in the same process node.

Overcoming process limitations used for your advanced ASIC lets your next generation solution get to market sooner.

Parameters

56G per Lane SerDes
  • 64 lanes with PAM4, LR on the Line Side
  • Low-power BoW with XSR on the Host Side
  • Retimer Function
  • 28nm process
112G per Lane SerDes
  • 32 Lanes with PAM4, MR+ on the Line Side
  • 32 Lanes with PAM4, XSR on the Host Side
  • 12nm process

Features

  • Switch Fabric ASIC
  • AI ASIC
  • Machine Learning ASIC
  • CPO Support

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