SerdES IP

Complete your custom Switch Fabric, AI, or HPC ASIC with Credo’s advanced SerDes IP. Our proven, innovative architecture is designed in TSMC’s 28nm, 16/12nm, and 7nm processes. Whether you’re moving from 28G to 56G or 112G, we have SerDes IP for you. Credo designs SerDes IP that delivers industry-leading performance and power, but are manufactured in lower risk, lower cost mature processes.

Parameters

  • 28G NRZ MR, LR in 28nm, 16/12nm, and 7nm processes
  • 56G PAM4 VSR, MR, LR in 16/12nm and 7nm processes
  • 112G PAM4 XSR, VSR, MR, LR in 16/12nm and 7nm processes
  • 10dB to 35dB bump-to-bump insertion loss

Features

  • Integrated PLL
  • Robust clock distribution architecture
  • Advanced mixed signal analog equalization architecture
  • Fully adaptive and programmable RX equalization
  • Auto-negotiation
  • Link Training
  • Excellent random jitter performance
  • Robust clock data recovery
  • Complete diagnostic suite
  • On-chip PRBS generation and checking
  • RX eye monitor
  • Loop back testing
  • JTAG/IEEE 1500
  • MCU per lane

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