Portal
Credo Logo

SerdES IP

Complete your custom Switch Fabric, AI, or HPC ASIC with Credo’s advanced SerDes IP. Our proven, innovative architecture is designed in TSMC’s 28nm, 16/12nm, N7/N6, N5/N4 and N3 processes. Whether you’re moving from 28G to 56G or 112G, we have SerDes IP for you. Credo designs SerDes IP that delivers industry-leading performance and power, but are manufactured in lower risk, lower cost mature processes.

Parameters

  • 28G NRZ MR, LR in 28nm, 16/12nm, N7/N6, N5/N4 and N3 processes
  • 56G PAM4 XSR, VSR, MR, LR in 16/12nm, N7/N6, N5/N4 and N3 processes
  • 112G PAM4 XSR, VSR, MR, LR in 16/12nm, N7/N6, N5/N4 and N3 processes
  • From a few dB to 35dB bump-to-bump insertion loss

Features

  • Integrated PLL
  • Robust clock distribution architecture
  • Advanced mixed signal analog or DSP equalization architectures
  • Fully adaptive and programmable RX equalization
  • Auto-negotiation
  • Link Training
  • Excellent random jitter performance
  • Robust clock data recovery
  • Complete diagnostic suite
  • On-chip PRBS generation and checking
  • RX monitors
  • Loop back testing
  • JTAG/IEEE 1500
  • MCU per lane

Let's Connect

Product Form
chevron-down