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Feb. 1, 2024

Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology

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Aug. 17, 2022

Credo Launches Comprehensive Family of 112G PAM4 SerDes IP for TSMC N5 and N4 Process Technologies

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Jun. 2, 2022

Credo Introduces Industry Leading 40Gbps PAM3 SerDes Technology To Address New Markets Requiring High-speed, Low-Power Connectivity

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Dec. 1, 2021

New Credo 3.2Tbps DSP Connectivity Chiplet with 56Gbps Lane Rates to Accelerate Time-to-Market for New Multi-chip Module ASICs

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May. 19, 2021

Credo Announces 3.2Tbps XSR-Enabled High-Speed Connectivity Chiplet with 112Gbps Lane Rates

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May. 24, 2019

Credo First to Demonstrate 7nm, 112G XSR SerDes

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Oct. 29, 2018

Credo First to Publicly Demonstrate 112G SerDes in 7nm at TSMC’s 2018 China OIP Forum

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Oct. 3, 2018

Credo to Showcase 56Gbps and 112Gbps SerDes at TSMC’s 2018 Open Innovation Platform Ecosystem Forum

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