Category: IP/Chiplet

Feb. 22, 2024

Chiplet Summit 2024: Opportunities, Challenges, and the Path Forward for Chiplets

Feb. 1, 2024

Credo Launches 112G PAM4 SerDes IP for TSMC N3 Process Technology

Jun. 26, 2023

Unleashing Innovation and Energy Efficiency at TSMC Events

Aug. 17, 2022

Credo Launches Comprehensive Family of 112G PAM4 SerDes IP for TSMC N5 and N4 Process Technologies

Aug. 17, 2022

IP Product Overview Video

Jun. 2, 2022

Credo Introduces Industry Leading 40Gbps PAM3 SerDes Technology To Address New Markets Requiring High-speed, Low-Power Connectivity

Dec. 1, 2021

New Credo 3.2Tbps DSP Connectivity Chiplet with 56Gbps Lane Rates to Accelerate Time-to-Market for New Multi-chip Module ASICs

May. 19, 2021

Credo Announces 3.2Tbps XSR-Enabled High-Speed Connectivity Chiplet with 112Gbps Lane Rates

May. 24, 2019

Credo First to Demonstrate 7nm, 112G XSR SerDes

Feb. 14, 2019

7 nanometer and Chiplets to Drive Ethernet Switch Market in 2019; Will Enable Second Generation 400 Gbps Capable of Longer Distances

Oct. 29, 2018

Credo First to Publicly Demonstrate 112G SerDes in 7nm at TSMC’s 2018 China OIP Forum

Oct. 3, 2018

Credo to Showcase 56Gbps and 112Gbps SerDes at TSMC’s 2018 Open Innovation Platform Ecosystem Forum